1. Field of the Invention
The present invention generally relates to a structure and method for measuring misalignments or overlay error between patterns created on a wafer during the fabrication process of an integrated circuit chip, and more specifically to measuring and controlling single nanometer alignment and overlay error components.
2. Description of Related Art
As the total alignment and overlay budget in the fabrication of advanced semiconductor circuits approach the nanometer regime, there is a concomitant need to measure and control single nanometer alignment and overlay error components. Current alignment and overlay techniques have not been shown to be adequate for the state-of-the-art small scale designs.
During the integrated circuit fabrication process, a number of patterned layers are formed on each other, typically using a photolithographic technique. The placement accuracy of each successive layer must be assessed and its precision controlled, otherwise misalignments will induce errors in the final product. The ultimate placement precision, or cumulative difference between patterns from various mask levels, is commonly referred to as xe2x80x9coverlay error.xe2x80x9d
Prior art techniques used to measure the amount of misalignment include using alignment marks which are typically box-shaped or cross-shaped, and matching subsequent mask layer alignment marks with the alignment mark of the first layer, or using a moiŕe fringe technique where the alignment marks are large areas filled with a regular pattern of small lines or dots. Two major contributors to overlay misalignment are related to the failures of symmetry of the overlay measurement tool and of the mark.
Errors in overlay measurements include tool induced shift (TIS) errors attributed to the metrology tool being utilized. Errors of this kind can be traced to asymmetries of tool components, e.g., camera, illumination misalignment, residual asymmetric aberrations, and the like. Tool asymmetry leads to biased overlay estimates, even on symmetric overlay measurement marks.
Another major source of overlay errors is traceable to asymmetries in the mark structure itself. Asymmetry in the mark definition has been shown to result in overlay inaccuracies averaging in excess of 70 to 200 nm.
The instant invention overcomes the major problems associated with current overlay and alignment structures and metrology, including the following: 1) insensitivity to alignment and overlay errorxe2x80x94Current practice measures the relative position of isolated pattern edges where only unity amplification is possible; 2) inefficient use of spacexe2x80x94Isolated patterns used in current practice make very inefficient use of the available space, resulting in large targets and inadequate signal to noise; 3) susceptibility to noisexe2x80x94The isolated patterns of conventional targets result in signals that are not conducive to spatial filtering; and, 4) incompatibility with product designsxe2x80x94The pattern density and feature size incompatibility of conventional targets with the active chip area makes it susceptible to process anomalies that introduce measurement error (commonly referred to as wafer induced shift or WIS).
In U.S. Pat. No. 6,061,606, entitled xe2x80x9cGEOMETRIC PHASE ANALYSIS FOR MARK ALIGNMENT,xe2x80x9d issued to Ross on May 9, 2000, a method of measuring overlay error using pairs of arrays having identical periodicity is disclosed. The spatial offset between the arrays is determined by Fourier Transform techniques. In this method, the combination of alignment arrays is digitized and Fourier Transformations are performed on the digital array pattern. Subsequent mathematical shifting and averaging is then used as a means of measuring the overlay error in two dimensions. Importantly, a Fourier Transform of the stored image of a combined alignment array must be calculated. The Fourier Transform is manipulated mathematically in order to determine the overlay error. This is achieved because information about the overlay error is represented within the Fourier Transform. While the use of arrays enables the application of Fourier Transform techniques, the use of a single periodicity limits the ability to distinguish the arrays, forcing the use of a side-by-side mark design that is inherently asymmetric and susceptible to TIS error, and constrains the sensitivity to overlay error to unity amplification. By using arrays of differing periodicity, however, the instant invention enables a symmetric interleaved mark design that greatly amplifies sensitivity to overlay error. Furthermore, the measurement of this mark does not require the complexity of Fourier analysis.
The invention described below is significantly different from the Ross invention, the moiŕe technique, and other conventional techniques, in that it uses a unique alignment mark combined with mathematical analysis that are not necessarily based on Fourier Transform applications to amplify the overlay error measurement.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and structure for measuring the alignment error between a mask and wafer and the overlay error between a plurality of masks.
It is another object of the present invention to provide a method and structure for measuring the overlay error using a more efficient and less complex image processing algorithm.
A further object of the invention is to provide a method and structure for measuring the relative position of interleaved arrays of differing periodicity and known geometric phase-shift, and amplifying the measured sensitivity.
It is yet another object of the present invention to provide a method and structure for measuring the overlay error and simultaneously maximizing space utilization and signal-to-noise ratio.
It is another object of the present invention to provide a method and structure for measuring the overlay error while enabling both analog and digital spatial filtering for noise suppression.
A further object of the present invention is to provide a method and structure for measuring the overlay error that enables target designs that closely mimic the density and feature size of the product.
Still other advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method for measuring and amplifying an overlay error between masked array patterns on a wafer during semiconductor fabrication, comprising: digitizing the array patterns to form a digitized image of the array patterns; interleaving the digitized image; determining a beat signal from the digitized image; calculating a zero-crossing of the beat signal; and, deriving overlay error using a proportionality constant of the zero-crossing calculation as an amplifying factor. The array patterns comprise different geometric periodicities and are phase shifted with respect to one another. The method further comprises calculating the proportionality constant as a function of the zero crossing of the beat signal and the geometric periodicities.
In a second aspect, the instant invention is directed to a method for measuring and amplifying overlay error between array patterns in a semiconductor wafer process, each of the array patterns having a pitch and a fundamental spatial frequency, the method comprising: applying the overlays as masks in subsequent layers in the process; forming a digital image of the array patterns, the digital image having intensity information in at least two-dimensions; integrating the intensity information; calculating a reference location of the integrated intensity information; obtaining the synthetic beat frequency zero-crossing from the reference location; and, calculating and analytically amplifying the overlay error using the zero-crossing. The array patterns are two dimensional, having different geometric periodicity, and are phase shifted with respect to one another, the geometric periodicity of each of the array patterns being inversely related to the fundamental spatial frequency. The digital image may be acquired by conventional microscopy and digitally captured by an electronic camera. The integrated intensity is determined separately in each axis orientation of the two-dimensional array pattern, and summed separately along each of the axis. The zero-crossing of the synthetic beat frequency is a function of the fundamental spatial frequencies of the arrays and the overlay error, such that the zero-crossing relates to an amplification of the overlay error. The method further comprises the amplification of the overlay error expressed as a fraction having a numerator and a denominator, the numerator represented by the spatial frequency of one of the arrays, and the denominator represented by a difference between the spatial frequencies of the arrays. Also, spatial filtering may be employed on the intensity information, such that fundamental frequencies and higher order harmonics of the intensity information may be calculated and eliminated.
In a third aspect, the instant invention is directed to an apparatus for measuring overlay error on a semiconductor wafer, comprising: a first alignment array having a first periodicity and a first spatial frequency, for masking on the semiconductor wafer; a second alignment array having a second periodicity and a second spatial frequency, for masking over the first alignment array on the semiconductor wafer; a conventional microscopy system adapted to optically image the first and second arrays; an electronic camera adapted to digitize the optical image; and, a microprocessor based system adapted to receive the digitized optical image and adapted to perform mathematical manipulations on the digitized optical image, the mathematical manipulations including calculating a synthetic beat frequency zero-crossing and a proportionality constant related to the overlay error.
In a fourth aspect, the instant invention is directed to a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform the method steps for calculating and amplifying overlay error between aligned array patterns during semiconductor fabrication, the method steps comprising: digitizing the array patterns to form a digitized image of the array patterns; interleaving the digitized image; calculating a phase shift from the digitized image; determining a beat signal from the digitized image; calculating a zero-crossing of the beat signal; and, amplifying the overlay error using a proportionality constant of the zero-crossing calculation as an amplifying factor.
In a fifth aspect, the instant invention is directed to a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform the method steps for calculating and amplifying overlay error between aligned array patterns during a semiconductor process, each of the array patterns having a pitch and a fundamental spatial frequency, the method steps comprising: applying the overlays as two dimensional array patterns in subsequent layers in the process; forming a digital image of the array patterns, the digital image having intensity information in at least two-dimensions; integrating the intensity information; calculating a reference location of the integrated intensity information; obtaining the synthetic beat frequency zero-crossing from the reference location; and, calculating and analytically amplifying the overlay error using the zero-crossing.
In a sixth aspect, the present invention is directed to a computer program product comprising: a computer usable medium having computer readable program code means embodied therein for causing calculation and amplification of overlay error between aligned array patterns during semiconductor fabrication, the computer readable program code means in the computer program product comprising: computer readable program code means for causing a computer to effect digitizing the array patterns to form a digitized image of the array patterns; computer readable program code means for causing a computer to effect interleaving the digitized image; computer readable program code means for causing a computer to effect calculating a phase shift from the digitized image; computer readable program code means for causing a computer to effect determining a beat signal from the digitized image; computer readable program code means for causing a computer to effect calculating a zero-crossing of the beat signal; and, computer readable program code means for causing a computer to effect amplifying the overlay error using a proportionality constant of the zero-crossing calculation as an amplifying factor.
In a seventh aspect, the present invention is directed to a computer program product comprising: a computer usable medium having computer readable program code means embodied therein for causing calculation and amplification of overlay error between aligned array patterns during a semiconductor process, each of the array patterns having a pitch and a fundamental spatial frequency, the computer readable program code means in the computer program product comprising: computer readable program code means for causing a computer to effect applying the overlays as two dimensional array patterns in subsequent layers in the process; computer readable program code means for causing a computer to effect forming a digital image of the array patterns, the digital image having intensity information in at least two-dimensions; computer readable program code means for causing a computer to effect integrating the intensity information; computer readable program code means for causing a computer to effect calculating a reference location of the integrated intensity information; computer readable program code means for causing a computer to effect obtaining the synthetic beat frequency zero-crossing from the reference location; and, computer readable program code means for causing a computer to effect calculating and analytically amplifying the overlay error using the zero-crossing.